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| ENTRY(__cpu_setup) tlbi vmalle1 dsb nsh
mov x0, #3 << 20 msr cpacr_el1, x0 mov x0, #1 << 12 msr mdscr_el1, x0 isb enable_dbg reset_pmuserenr_el0 x0
ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \ MAIR(0x04, MT_DEVICE_nGnRE) | \ MAIR(0x0c, MT_DEVICE_GRE) | \ MAIR(0x44, MT_NORMAL_NC) | \ MAIR(0xff, MT_NORMAL) | \ MAIR(0xbb, MT_NORMAL_WT) msr mair_el1, x5
adr x5, crval ldp w5, w6, [x5] mrs x0, sctlr_el1 bic x0, x0, x5 orr x0, x0, x6
ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 tcr_set_idmap_t0sz x10, x9
mrs x9, ID_AA64MMFR0_EL1 bfi x10, x9, #32, #3 #ifdef CONFIG_ARM64_HW_AFDBM
mrs x9, ID_AA64MMFR1_EL1 and x9, x9, #0xf cbz x9, 2f cmp x9, #2 b.lt 1f orr x10, x10, #TCR_HD 1: orr x10, x10, #TCR_HA 2: #endif msr tcr_el1, x10 ret ENDPROC(__cpu_setup)
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